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'synth_intel' command,synthesis result is wrong
pending-verification
This issue is pending verification and/or reproduction
#4673
opened Oct 17, 2024 by
CL-liao
cxxopts migration broke Tcl argument passing
pending-verification
This issue is pending verification and/or reproduction
#4669
opened Oct 16, 2024 by
povik
misc/yosys-config.in uses an non-portable test(1) operator
pending-verification
This issue is pending verification and/or reproduction
#4665
opened Oct 14, 2024 by
thorpej
Assert
flow.wire_comb_defs[it].size() == 1
in write_cxxrtl
bug
cxxrtl
#4664
opened Oct 14, 2024 by
rroohhh
Verilog globals appended to modules instead of prepended
pending-verification
This issue is pending verification and/or reproduction
#4653
opened Oct 10, 2024 by
jmi2k
FSM pass equivalence bug
pending-verification
This issue is pending verification and/or reproduction
#4651
opened Oct 10, 2024 by
joonho3020
sta
command hangs on some designs
pending-verification
#4648
opened Oct 9, 2024 by
lukbau
write_btor: Part selects of undriven signals are lowered as separate inputs
pending-verification
This issue is pending verification and/or reproduction
#4640
opened Oct 8, 2024 by
georgerennie
Co-simulation fails for $fa cell
pending-verification
This issue is pending verification and/or reproduction
#4638
opened Oct 7, 2024 by
RCoeurjoly
tee -q -o <bad-path>
fails silently
pending-verification
#4636
opened Oct 7, 2024 by
povik
Synthesis fails on MacOS but succeeds on Linux (possibly ABC error)
pending-verification
This issue is pending verification and/or reproduction
#4618
opened Sep 29, 2024 by
agrif
VCD file parsing error in sim pass with GHDL-generated VCDs due to whitespace handling
pending-verification
This issue is pending verification and/or reproduction
#4617
opened Sep 27, 2024 by
RCoeurjoly
Yosys Synthesis Fails with std::out_of_range Error in OPT_DEMORGAN Pass
pending-verification
This issue is pending verification and/or reproduction
#4610
opened Sep 24, 2024 by
LoSyTe
Nanoxplore synthesis does not works when using abc9 flow
pending-verification
This issue is pending verification and/or reproduction
#4606
opened Sep 19, 2024 by
samhanic
Port names starting with '%' cause stack buffer overflow during error reporting
pending-verification
This issue is pending verification and/or reproduction
#4599
opened Sep 13, 2024 by
mattyoung101
verific: wrong source attribute for $add cell with binary literal operand
pending-verification
This issue is pending verification and/or reproduction
#4597
opened Sep 12, 2024 by
RCoeurjoly
Inconsistency with how libyosys is imported in Python
feature-request
#4591
opened Sep 9, 2024 by
donn
Synthesis with synth_xilinx crashes in TECHMAP pass
pending-verification
This issue is pending verification and/or reproduction
#4590
opened Sep 9, 2024 by
marzoul
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