sta command hangs on some designs

[lukbau]

Version

Yosys 0.45+240 (git sha1 b4fd8e7, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

run with hanging

1. open yosys with yosys -m ghdl
2. load the design ghdl faulty.vhd -e faulty
3. run synthesis e.g synth_ecp5
4. run sta sta

run without hanging

1. comment out the line 44 and comment in line 45
2. do the steps as described above

Here is the file that was used for testing. After download rename it to faulty.vhd
faulty.vhd

When waiting for a longer period of time yosys starts printing the latest arrival time, followed by the same repeating messages indefinitely. (starting at line 1242)
faulty.log

Expected Behavior

The sta command should run for any synthesized design without going into an infinite loop.

Actual Behavior

the sta command hangs when using it on a finite state machine where the state transition is dependent on a signal of another process. If the signals that controls the transition is coming form outside of the module the sta command runs without any issue.