[pull] master from YosysHQ:master

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[todo]

for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed

nextpnr/fpga_interchange/globals.cc

Lines 161 to 166 in 432b9d8

	// TODO: for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed
	// before the GBs it drives
	for (auto cell : sorted(ctx->cells)) {
	CellInfo *ci = cell.second;
	const GlobalCellPOD *glb_cell = global_cell_info(ci->type);
	if (glb_cell == nullptr)

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This comment was generated by todo based on a TODO comment in 432b9d8 in #258. cc @YosysHQ.

[todo]

substantial performance improvements are probably possible, although of questionable benefit given

nextpnr/fpga_interchange/globals.cc

Lines 200 to 205 in 432b9d8

	// TODO: substantial performance improvements are probably possible, although of questionable benefit given
	// the low number of globals in a typical device...
	BelId best_bel;
	int shortest_distance = std::numeric_limits<int>::max();
	for (auto bel : getBels()) {

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This comment was generated by todo based on a TODO comment in 432b9d8 in #258. cc @YosysHQ.