GitHub - Cadynum/cell-fpga: 1D binary cellular automata implemented on Xilinx Spartan 6

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1D binary cellular automata implemented on Xilinx Spartan 6

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Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
Nexys3_Master.ucf		Nexys3_Master.ucf
cell.vhd		cell.vhd
cell1d.vhd		cell1d.vhd
celltest.vhd		celltest.vhd
clockgen.vhd		clockgen.vhd
debounce.vhd		debounce.vhd
decimal7seg.vhd		decimal7seg.vhd
onepulse.vhd		onepulse.vhd
readme		readme
vgacontroller.vhd		vgacontroller.vhd
vgatest.vhd		vgatest.vhd

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Cellular automata tested on digilent nexys3 spartan 6.


Set DCM to output 65Mhz

1D binary cellular automata implemented on Xilinx Spartan 6

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