Add PDK support status to Readme + update to OpenLane 2.0.0b16

Also fix `unplace.py`, remove `fill_cells.yml` which is now redundant

Readme.md

@@ -12,70 +12,104 @@
 Standard Cell Library based Memory Compiler using DFF/Latch cells.
 
 # ✨ Installation & Usage
-See [this document](./docs/Usage.md). 
 
-You can try the [Google Colaboratory](https://colab.research.google.com/github/Cloud-V/DFFRAM/blob/main/dffram.ipynb),
+See [this document](./docs/Usage.md).
+
+You can try the
+[Google Colaboratory](https://colab.research.google.com/github/Cloud-V/DFFRAM/blob/main/dffram.ipynb),
 but it is a bit out-of-date at this point.
 
+## Platform Support Status
+
+| Configured Platform | Working | Silicon-proven\* |
+| - | - | - |
+| `sky130A` | Yes | Yes |
+| `sky130B` | Yes | No |
+| `gf180mcuD` | No\* (Hold violations in the Netlist) | No |
+
+> \* Silicon proven does not imply that you should use it without whole-system,
+> timing-annotated simulation to make sure that it works for your circuit.
+>
+> There may be design-specific complications that may render DFFRAM (and indeed
+> the entire chip) unusable. Proceed with caution.
+
 # Overview
-The objective of this project is to develop a DFF/Latch-based RAM, Register File and Cache custom compilation flow that utilizes standard cell libraries following a standard ASIC (Application Specific Integrated Circuit) implementation approach. Different views (HDL netlist, HDL functional models, LEF, GDS, Timing, …) are all generated for a given size configuration.
 
-The layout targets highly compact designs (85%+) as the cells are placed on the floor plan using a custom placer. Moreover, the custom placer ensures that the routing will be relatively simple. Currently, the compiler uses OpenROAD routers to route the macros with great success. 
+The objective of this project is to develop a DFF/Latch-based RAM, Register File
+and Cache custom compilation flow that utilizes standard cell libraries
+following a standard ASIC (Application Specific Integrated Circuit)
+implementation approach. Different views (HDL netlist, HDL functional models,
+LEF, GDS, Timing, …) are all generated for a given size configuration.
 
-The Compiler relies on basic building blocks to construct the layout of different RAM/RF/Cache configurations. Check [the compiler documentation](./docs/) for more info. The following shows how a 32x32 memory (DFF based) is constructed.
+The layout targets highly compact designs (85%+) as the cells are placed on the
+floor plan using a custom placer. Moreover, the custom placer ensures that the
+routing will be relatively simple. Currently, the compiler uses OpenROAD routers
+to route the macros with great success.
+
+The Compiler relies on basic building blocks to construct the layout of
+different RAM/RF/Cache configurations. Check
+[the compiler documentation](./docs/) for more info. The following shows how a
+32x32 memory (DFF based) is constructed.
 
 ![](./docs/img/ram_ex.png)
 
-The generated layouts by the DFFRAM compilers for RAM32 as well as its building blocks are as follows:
-- First, a byte, which is just 8 bits placed together...
-![GDS layout of a byte](./docs/img/1x8.png)
+The generated layouts by the DFFRAM compilers for RAM32 as well as its building
+blocks are as follows:
 
-- Put four of those side by side, and you get a 32-bit word...
-![GDS layout of a word](./docs/img/1x32.png)
+* First, a byte, which is just 8 bits placed together...
+  ![GDS layout of a byte](./docs/img/1x8.png)
 
-- Stack eight of those for an 8 word bank of RAM...
-![GDS layout of 8 words stacked vertically](./docs/img/8x32.png)
+* Put four of those side by side, and you get a 32-bit word...
+  ![GDS layout of a word](./docs/img/1x32.png)
 
-- And stack 4 of these 8 words for a kilobit of RAM!
-![GDS layout of 4x8 words stacked vertically](./docs/img/32x32.png)
+* Stack eight of those for an 8 word bank of RAM...
+  ![GDS layout of 8 words stacked vertically](./docs/img/8x32.png)
 
-- We can keep going, but these images aren't getting any smaller. As a bonus though, here is 64 kilobits:
-![8kbytes](./docs/img/8kb_layout.png)
+* And stack 4 of these 8 words for a kilobit of RAM!
+  ![GDS layout of 4x8 words stacked vertically](./docs/img/32x32.png)
 
-> That stuff you see on the right of each image? It's clock gates, decoders and the like. Don't worry about it.
+* We can keep going, but these images aren't getting any smaller. As a bonus
+  though, here is 64 kilobits: ![8kbytes](./docs/img/8kb_layout.png)
 
+> That stuff you see on the right of each image? It's clock gates, decoders and
+> the like. Don't worry about it.
 
 Currently, the can compiler generate the layout of the following configurations:
 
 > 1RW1R variants are temporarily disabled due to a bug.
 
-- RAM
-  - 32 words with byte write enable (1RW and 1RW1R).
-  - 128 words with byte write enable (1RW and 1RW1R).
-  - 256 words with byte write enable (1RW and 1RW1R).
-  - 512 words with byte write enable (1RW and 1RW1R).
-  - 1024 words with byte write enable (1RW and 1RW1R).
-  - 2048 words with byte write enable (1RW and 1RW1R).
-- Register File
-  - 32 x 32-bit words (2R1W)
-
-The [`OpenLane/`](./OpenLane) folder will contain good known OpenLane configurations to build DFFRAM different macros. 
-
+* RAM
+  * 32 words with byte write enable (1RW and 1RW1R).
+  * 128 words with byte write enable (1RW and 1RW1R).
+  * 256 words with byte write enable (1RW and 1RW1R).
+  * 512 words with byte write enable (1RW and 1RW1R).
+  * 1024 words with byte write enable (1RW and 1RW1R).
+  * 2048 words with byte write enable (1RW and 1RW1R).
+* Register File
+  * 32 x 32-bit words (2R1W)
+
+The [`OpenLane/`](./OpenLane) folder will contain good known OpenLane
+configurations to build DFFRAM different macros.
+
 ## File Structure
+
 * `.github` contains files for GitHub actions.
 * `docs/` contains documentation (😮)
-* `rtl/` contains RTL RAM file generators for benchmarking and comparison purposes.
+* `rtl/` contains RTL RAM file generators for benchmarking and comparison
+  purposes.
 * `platforms/` contains PDK-specific files:
   * `<pdk-name>/`
     * `<scl-name>/`
-      * `_building_blocks/` contains a hierarchy of building blocks supported by the compiler.
+      * `_building_blocks/` contains a hierarchy of building blocks supported by
+        the compiler.
 * `placeram/` is the custom placer Python module.
 * `scripts/` has assisting scripts used by the flow.
 * `dffram.py` is the compilation flow going from building blocks to LVS.
 
 # Comparisons
-The following table compares the areas and bit densities of RAM macros generated using different means.
 
+The following table compares the areas and bit densities of RAM macros generated
+using different means.
 
 <table>
   <tr>
@@ -118,8 +152,8 @@ The following table compares the areas and bit densities of RAM macros generated
     <td> 1,584.24 x 788.8 </td> <td> 26,196 </td>
     <td> 1940.45 x 1951.17 </td> <td> 8,654 </td>
     <td> 2,074 x 2,085 </td> <td> 7,578 </td>
-    
-  </tr>
+
+</tr>
   <tr>
     <td> 8 kbytes </td>
     <td> N/A </td> <td> N/A </td>
@@ -129,25 +163,27 @@ The following table compares the areas and bit densities of RAM macros generated
   </tr>
 </table>
 
-
-
-<sup>1</sup> All support 32-bit word reads and 1, 2, and 4 bytes writes.  
-<sup>2</sup> Values are based on the original layout produced by the compiler. OpenRAM macros are typically wrapped to be useful w/ automated PnR ASIC flows.
+<sup>1</sup> All support 32-bit word reads and 1, 2, and 4 bytes
+writes.\
+<sup>2</sup> Values are based on the original layout produced by the
+compiler. OpenRAM macros are typically wrapped to be useful w/ automated PnR
+ASIC flows.
 
 # ⚖️ Copyright and Licensing
+
 <a id="copyright-and-licensing"></a>
 
 Copyright ©2020-2023 The American University in Cairo
 
-Licensed under the Apache License, Version 2.0 (the "Open Source License");
-you may not use this file except in compliance with the Open Source License.
-You may obtain a copy of the Open Source License at the root of this repository
-(see the file 'License') or at
+Licensed under the Apache License, Version 2.0 (the "Open Source License"); you
+may not use this file except in compliance with the Open Source License. You may
+obtain a copy of the Open Source License at the root of this repository (see the
+file 'License') or at
 
 > http://www.apache.org/licenses/LICENSE-2.0
 
-Unless required by applicable law or agreed to in writing, software
-distributed under the Open Source License is distributed on an "AS IS" BASIS,
-WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the Open Source License for the specific language governing permissions and
-limitations under the Open Source License.
+Unless required by applicable law or agreed to in writing, software distributed
+under the Open Source License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the Open
+Source License for the specific language governing permissions and limitations
+under the Open Source License.

dffram.py

@@ -242,6 +242,7 @@ def main(
     default_clock_period,
     min_height,
     flow_name,
+    pdk_root,
     **kwargs,
 ):
     if variant == "DEFAULT":
@@ -358,6 +359,7 @@ def main(
             "DESIGN_IS_CORE": False,
         },
         design_dir=os.path.abspath(build_dir),
+        pdk_root=pdk_root,
     )
 
     final_state = dffram_flow.start(

requirements.txt

@@ -1,3 +1,3 @@
-openlane==2.0.0b14
+openlane==2.0.0b16
 pyyaml
-cloup
+cloup

scripts/python/unplace.py

@@ -32,29 +32,43 @@
 
 @click.command()
 @click.option(
-    "-p", "--platform", required=True, help="PDK/Platform to use, e.g. sky130A"
+    "-p",
+    "--platform",
+    required=True,
+    help="Platform (PDK) to use",
+)
+@click.option(
+    "-s",
+    "--scl",
+    required=True,
+    help="SCL to use in the format",
 )
 @click.option(
     "-o",
     "--output",
     "output_file",
+    type=click.Path(file_okay=True, dir_okay=False),
     default="/dev/stdout",
     help="Output file",
     show_default=True,
 )
-@click.argument("input_file", required=True)
-def unplace(platform, output_file, input_file):
+@click.argument(
+    "input_file",
+    type=click.Path(file_okay=True, dir_okay=False, exists=True),
+    required=True,
+)
+def unplace(platform: str, scl: str, output_file: str, input_file: str):
     dn = os.path.dirname
     dffram_path = dn(dn(dn(os.path.abspath(__file__))))
-    fill_yml_path = os.path.join(dffram_path, "platforms", platform, "fill_cells.yml")
+    tech_path = os.path.join(dffram_path, "platforms", platform, scl, "tech.yml")
     try:
-        fill_yml_str = open(fill_yml_path).read()
+        tech_str = open(tech_path).read()
     except FileNotFoundError:
-        print(f"{fill_yml_path} not found.", file=sys.stderr)
+        print(f"{tech_path} not found.", file=sys.stderr)
         exit(os.EX_NOINPUT)
 
-    data: dict = yaml.load(fill_yml_str, Loader=yaml.SafeLoader)
-    rx_list = list(data.values())
+    data: dict = yaml.load(tech_str, Loader=yaml.SafeLoader)
+    rx_list = list(data["fills"].values())
 
     try:
         input_str = open(input_file).read()

shell.nix

@@ -12,14 +12,12 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 {
-    pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/0218941ea68b4c625533bead7bbb94ccce52dceb.tar.gz") {}
+    pkgs ? import <nixpkgs> {}
 }:
 
 let openlane-src = pkgs.fetchFromGitHub {
     owner = "efabless";
     repo = "openlane2";
-    rev = "0c05b7ea04eac74203a9a33f8a8b519f33220f2f";
-    sha256 = "sha256-fjYz6HuIYrGbkb1oA6wPIlEjieYU5hu0aygYQFj2d2I=";
-}; in import "${openlane-src}/shell.nix" {
-    inherit pkgs;
-}
+    rev = "83ec6c32add40006cc70d951745667d30193f51d";
+    sha256 = "sha256-9Xms6eRf3yyaFJVVjk+uPYYM+EDRl4GYAYYUK5QhiLc=";
+}; in import "${openlane-src}/shell.nix" {}