Atomic access to multi-block registers - holding register documentation

[m-kru]

In Atomic access to multi-block registers you state:

The advantage of sharing holding registers is that it reduces the size of the address decoder and read multiplexer; many addresses taking data from the same source is advantageous for both area and timing. The primary disadvantage is that it only works properly when the blocks are accessed sequentially and completely. It is up to the bus master to enforce this; if it fails to do so, accesses may end up reading or writing garbage. You can therefore generally NOT mix purely AXI4L multi-master systems with multi-block registers.

I am not sure you are correct here. With logical registers wider than the data bus width you still have multiple addresses, which you present, for example, here bitrange. The required address space size is not smaller because of the holding register, so how can it affect the address decoding logic? I think the only resource utilization you reduce by sharing the snapshot/shadow register (you call it holding register) is the number of flip flops required for logical registers wider than the data bus width.

[jvanstraten]

Sorry for the exceptionally late response. I broke my hand right around the time you posted this, couldn't type at the time, and then it slipped through the cracks. Better late than never I suppose.

Anyway, I think you're right and my thinking was flawed. Even thinking about it now my intuition is that it's smaller, but when I try drawing it out in my head it's indeed the same. Maybe it's advantageous for timing since you effectively get two sequential read multiplexers for the holding register, but it's probably negligible.

[jvanstraten]

It looks like whatever CI used to generate the docs is long gone, but I updated the sources, at least. I guess I'll keep this open then.

[mbrobbel]

It looks like whatever CI used to generate the docs is long gone, but I updated the sources, at least. I guess I'll keep this open then.

#14

[m-kru]

@jvanstraten

Maybe it's advantageous for timing since you effectively get two sequential read multiplexers for the holding register, but it's probably negligible.

If the slave has large number of registers it might be. However, I guess it also depends on the relative size of these 2 stage multiplexers. If any of the multiplexers is much bigger than the other one, than it probably again becomes negligible.