Support generation of FIFO / ring buffer style memories for queues

[mithro]

FIFOs and ring buffers are super useful to enable high performance transfer between things like DMA controllers and peripherals like video output / input systems or between CPUs and FPGAs or between various blocks found inside things like JPEG encoders.

The basic structure is;

• Any bit width -- 1 bit, 8 bits (IE a byte) and 32bits/64bits (IE 4 / 8 bytes) are common sizes
• 1 write port
• 1 read port

The actual memory addresses are not normally exposed, they can generally just be incremented / decremented by 1.
There is normally a signal which indicates if the write and read ports are pointing at the same address (or differ by a single value).

[donn]

@shalan Do you have a netlist for this usecase?